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DS26518DK octal t1/e1/j1 transceive r demo kit daughter card www.maxim-ic.com general description the DS26518DK is an easy -to-use evaluation board for the ds26518 octal t1/e1/j1 transceiver. the DS26518DK is a stand-alone system. the board comes complete with a tr ansceiver, transformers, termination resistors, conf iguration switches, network connectors, processor, rs-232 usb interface, and power adapter. dallas chipview software gives point-and-click access to configuration and status registers from a windows ? -based pc. on-board leds indicate receive loss-of-signal and interrupt status, as well as multiple clock and signal routing configurations. windows is a registered trademark of microsoft corp. demo kit contents DS26518DK daughter card 5.0v power adapter coax cable adapters usb cable cd_rom including: chipview software DS26518DK data sheet ds26518 data sheet ds26518 errata sheet (if applicable) features demonstrates key functions of ds26518 t1/e1/j1 sct includes transceiver, transformers, network connectors, termination passives and coaxial cables stand-alone demo kit on-board mmc2107 processor and chipview software provide point-and-click access to the ds26518register set software-controlled (register mapped) configuration switches to facilitate clock and signal routing all equipment-side framer pins are easily accessible for external data source/sink leds for loss-of-signal and interrupt status as well as indications for multiple clock and signal routing configurations easy-to-read silkscreen labels identify the signals associated with all connectors, jumpers, and leds ordering information part description DS26518DK demo kit daughter card for ds26518 1 of 40 rev: 011007 downloaded from: http:///
DS26518DK 2 of 40 table of contents 1. board floorplan ........................................................................................................3 2. pcb versions .................................................................................................................3 3. pcb errata .....................................................................................................................3 4. basic operation ...........................................................................................................4 4.1 h ardware c onfiguration ........................................................................................................... 4 4.1.1 general .................................................................................................................................................. 4 4.2 q uick s etup (r egister v iew ) ...................................................................................................... 4 4.2.1 miscellaneous ........................................................................................................................................ 4 5. test points and connectors .................................................................................5 6. address map ..................................................................................................................7 6.1 spi m ode ...................................................................................................................................... 7 6.2 fpga r egister m ap .................................................................................................................... 7 6.3 id r egisters ............................................................................................................................... .8 6.4 c ontrol r egisters ..................................................................................................................... 9 6.5 fpga c ontrol e xamples .......................................................................................................... 16 7. additional information/resources ..................................................................17 7.1 ds26518 i nformation ................................................................................................................ 17 7.2 DS26518DK i nformation ........................................................................................................... 17 7.3 t echnical s upport .................................................................................................................... 17 8. component list ..........................................................................................................18 9. schematics ..................................................................................................................19 list of tables table 5-1. test points and connectors ....................................................................................................................... 5 table 6-1. daughter card address map ...................................................................................................................... 7 table 6-2. fpga register map ................................................................................................................................... 7 table 6-3. refclkio source definition ..................................................................................................................... 9 table 6-4. mclk source definition ............................................................................................................................. 9 table 6-5. rsysclk source definition .................................................................................................................... 10 table 6-6. tsysclk source definition ..................................................................................................................... 10 table 6-7. tssync source definition ...................................................................................................................... 11 table 6-8. tclkx source definition .......................................................................................................................... 12 table 6-9. tsyncx source definition ....................................................................................................................... 13 table 6-10. rsyncx source definition ..................................................................................................................... 14 table 6-11. tserx source definition ........................................................................................................................ 15 table 6-12. fpga configuration (port 1, t1 mode) .................................................................................................. 16 table 6-13. ds26518 partial configuration (port 1, t1 mode) ................................................................................. 16 downloaded from: http:///
DS26518DK 3 of 40 1. board floorplan ds26518 fpga config prom fpga jtag clocks rlos 1 to 4 leds rlf 1 to 4 leds int led quad-port transformer 2.5v fpga supply tp port 4 tp port 3 tp port 2 tp port 1 tp port 8 tp port 7 tp port 6 tp port 5 quad-port transformer rlf 5 to 8 leds rlos 5 to 8 leds fpga status test points tssync, bpclk, refclk, mclk test points: rclkn, tclkn rsern, tsern rsyncn, tsyncn rchbkn, tchbkn rsign, tsign rmn ( n = port 5 to 8 ) test points: rclkn, tclkn rsern, tsern rsyncn, tsyncn rchbkn, tchbkn rsign, tsign rmn ( n = port 1 to 4 ) 1.8v core supply 3.3v board supply 5.0v dc 2. pcb versions there is one circuit board version for the ds26518 de mo kit. the part number should read DS26518DK01a0. 3. pcb errata DS26518DK01a0 11/11/2006: there are no errata for this board. jack sram mmc2107 processor once debug rs-232 57.6k 8-n-1-none uart usb to paralle l usb fifo downloaded from: http:///
DS26518DK 4 of 40 4. basic operation this demo kit relies upon several supporting files, which are available for downloading on our website at www.maxim-ic.com/DS26518DK quickview data sheet for these files. 4.1 hardware configuration ? supply 5.0v to the plug-in jack. ? configure the jumpers as detailed in table 5-1 . for quick setup steps listed below configure the device for motorola parallel port mode (this is determi ned by jumpers jp1-to-jp4 and jp8, jp9). 4.1.1 general upon power-up, the rlos leds (red) will be lit, the int led (red) will not be lit, and the fpga status led (ds1 green) will be lit. 4.2 quick setup (register view) 1) from the programs menu, launch the host application named chipview.exe . run the chipview application. if the default installation options were used, click the start button on the windows toolbar and select programs chipview chipview . 2) the pc loads chipview, offering a choice among demo mode, register view, and terminal mode. select register view. 3) the program will request a definition file. navigate to t he .def files in the t1 or e1 folder, then select the _DS26518DK01a0_fpga.def . note: through the links section, this will also load the ds26518 global .def file along with eight liu .def files and eight framer .def files. 4) the register view screen will appear, showing the register names, acronyms, and values for the ds26518. 5) predefined register settings for several func tions are available as initialization files. o .ini files are loaded by selecting the menu f ile m emory config file l oad mfg file . o load the .mfg file load_allslices_e1_75.mfg . 6) after loading the .mfg file , the following may be observed: o the ds26518 is in e1 mode and begins transmitting ais. o the rlos leds extinguish upon external loopback. rlf will remain lit. 4.2.1 miscellaneous 1) clock frequencies and port-to-por t connection are provided by a register-mapped fpga that is on the ds26518 daughter card. 2) the definition file for this fpga is named ds26518dc_fpga.def . see table 6-2 for the fpga register map definitions. a drop-down menu on the right of the screen allows for switching between definition files. 3) all files referenced above are available for download as described in the section marked basic operation. 4) configuration files for basic t1 bert operat ion are provided in the folder named t1_bert. 5) spi mode definition and configuratio n files are provided in the additi onal_def_files section. the ds26518 must be in spi mode when using these files (set jumpers jp1Cjp4 and jp8 per table 5-1 ). downloaded from: http:///
DS26518DK 5 of 40 6) files with ds26518 annotations are provided in the a dditional_def_files section. these files indicate bit level differences between the ds26518 and the ds26518. in these files the ds26518 bit name is provided in parentheses, followed by the ds26518 bit name. 5. test points and connectors the DS26518DK has several connectors, test points, oscillators, and jumpers. table 5-1 provides a description of these signals, given approximately in or der of appearance on the pcb, from left to right then top to bottom (with the board held so that the rs-232 connector is on the top edge). jumpers jp1 to jp11 do not have a pin 1 identifier on the top of the pcb. for these jumpers pin1 is identified by the square pad that is visible on the pc bs solder side. jp1 to jp11 pin 1 is on the left side of the pcb when the board is held so that the rs- 232 connector is on the top edge. table 5-1. test points and connectors silkscreen reference function default setting schematic page description j3 usb connector user decision 16 used for communication with host pc. when usb is used, the rs-232 port should not be used. drivers for the usb device are provided on the cd that ships with the demo kit. j02 rs-232 connector connected to host pc 16 used for communication with host pc. basic setting is 57.6k baud, 8 bits, no stop bit, 1 parity bit (57.6, 8, n, 1). when rs-232 is used, the usb port should not be used. j1 once bdm connector 16 once debug connector for mmc2107 processor j2 power supply v dd 5.0v 17 system v dd . always connected to power supply. sw1 system reset 15 system reset. connects to all device reset pins. jp1 cs selection jumpered pins 2+3 2 ds26518 chip-select selection. pins 2+3 are used for parallel port mode. pins 1+2 are used for spi mode. jp2 d0/miso selection jumpered pins 1+2 2 ds26518 data bus configuration. used to select between data bit 0 (pins 1+2) and spi miso (pins 2+3). jp3 d1/mosi jumpered pins 1+2 2 ds26518 data bus configuration. used to select between data bit 1 (pins 1+2) and spi mosi (pins 2+3). jp4 d2/spick jumpered pins 1+2 2 ds26518 data bus configuration. used to select between data bit 2 (pins 1+2) and spi sck (pins 2+3). jp5 spi swap bias jumpered pins 2+3 9 ds26518 spi swap (only relevant in spi mode). pull high to match processor defaults. jp6 spi cpha bias jumpered pins 2+3 9 ds26518 spi clock phase (only relevant in spi mode). pull to the same value as spi_cpol to match processor defaults. jp7 spi cpol bias jumpered pins 2+3 9 ds26518 spi clock polarity (only relevant in spi mode). pull to the same value as spi_cpha to match processor defaults. jp8 spi sel bias jumpered pins 1+2 9 ds26518 spi/parallel port selection. pins 1+2 are used for parallel port, pins 2+3 are used for spi mode. jp9 bts bias jumpered pins 2+3 9 ds26518 bus type selection. high for motorola mode. downloaded from: http:///
DS26518DK 6 of 40 silkscreen reference function default setting schematic page description jp10 txenable jumpered pins 2+3 9 ds26518 transmit enable. low for tri-state. jp11 digio enable jumpered pins 2+3 9 ds26518 digital i/o enable. low for tri-state. ds1 cfg ok on (green) 12 system configuration led. on when the system has been successfully configured. j5 flash vpp not installed flash vpp jumper. installed during erase and program of the mmc2107 j7 jtag testpoints 13 test points for ds26518 jtag. here the ds26518 is the only device in the chain. jtag for the fpga is provided on the same connector to facilitate chain concatenation. ds2 int ds26518 off (not red) 12 ds26518 interrupt status led. on when the ds26518 interrupt is active. j6 testpoints 10 ds26518 test points for tssync, bpclk, refclk and mclk ds3 led on (green) power ok led y2 oscillator not populated 12 spare oscillator yb2 (bottom side) oscillator 16.348mhz 12 provides e1 base rate. the fpga divides this clock by 8 to obtain 2.048mhz. yb1 (bottom side) oscillator 1.544mhz 12 provides t1 base rate j8, j9, j10, j12, j13, j14, j15 test points ports 2 to 8 10, 11 ds26518 test points for rclk, tclk, rser, tser, rsync, tsync, rchbk, tchbk, rsig, tsig, rm, tsysclk, rlos, rsysclk, rlf_led j11 test points port 1 10 ds26518 test points. similar to the test points for ports 2 to 8. several pins for port 1 have functions slightly different than the other ports. these pins are: al_flos, rlos, rlf_ltc, tsysclk, rsysclk. ds6, ds8, ds14, ds18, ds5, ds11, ds13, ds17 led (red) 10 ds26518 rlf leds ds7, ds9, ds15, ds19, ds4, ds10, ds12, ds16 led (red) 10 ds26518 rlos leds j16 to j23 jumper gnd not installed 5 to 8 ds26518 transmit ground strap. used to ground the tring side of ttip/tring. used for e1 mode with bnc connectors. j24 to j39 tip/ring jumper coax connector 5 to 8 ds26518 test points for ttip/tring and rtip/rring. a custom 2-pin to bnc cable is provided for this connection. jb1, jb2 (bottom side) rj45 rj45 5 to 8 ds26518 rj45 connectors downloaded from: http:///
DS26518DK 7 of 40 6. address map address space begins at 0x81000000. a ll offsets given in the following tables are relative to 0x81000000. registers in the fpga can be easily modified using the chipview host-based user interface software along with the definition file named ds26518dc_fpga.def. table 6-1. daughter card address map offset device description 0x0000 to 0x0087 fpga board identifi cation and clock/signal routing 0x4000 to 0x40ef ds26518 ds26518 framer 1 rx registers 0x40f0 to 0x40ff ds26518 ds26518 global registers 0x4100 to 0x41ef ds26518 ds26518 framer 1 tx registers 0x41f0 to 0x41ff ds26518 ds26518 reserved registers 0x4200 to 0x4fff ds26518 ds26518 framer 2 to 8 registers 0x5000 to 0x50ff ds26518 ds26518 liu 1 to 8 registers 0x5100 to 0x517f ds26518 ds26518 bert 1 to 8 registers 0x5180 to 0x5fff ds26518 ds26518 reserved registers 6.1 spi mode the ds26518 addresses shown in table 6-1 are for parallel port mode. when spi mode is selected the ds26518 base address begins at 0x00. for spi mode chipview requires a separate set of definition files, which are provided along with the def files for parallel port mode. table 5-1 details the default bias levels for spi configuration pins. to change these settings, the processors spi settings must al so change. the processor spi settings can be changed in chipviews terminal mode using the spisg s function. 6.2 fpga register map table 6-2. fpga register map offset register name type description 0x0000 bid read-only board id 0x0002 xbidh read-only high nibble extended board id 0x0003 xbidm read-only middle nibble extended board id 0x0004 xbidl read-only low nibble extended board id 0x0005 brev read-only board fab revision 0x0006 arev read-only board assembly revision 0x0007 prev read-only pld revision 0x0011 csr control ds26518 mclk and refclkio source 0x0012 0x0022 0x0032 0x0042 0x0052 0x0062 0x0072 0x0082 sysclk_trn (n = 8 to 1) control ds26518 tx and rx sysc lk source, ports 8 to 1 0x0013 synctss control ds26518 tssync source downloaded from: http:///
DS26518DK 8 of 40 offset register name type description 0x0014 0x0024 0x0034 0x0044 0x0054 0x0064 0x0074 0x0084 tcsrn (n = 8 to 1) control ds26518 tclk source, ports 8 to 1 0x0015 0x0025 0x0035 0x0045 0x0055 0x0065 0x0075 0x0085 tsyncsn (n = 8 to 1) control ds26518 tsync source, ports 8 to 1 0x0016 0x0026 0x0036 0x0046 0x0056 0x0066 0x0076 0x0086 rsyncsrn (n = 8 to 1) control ds26518 rsync source select, ports 8 to 1 0x0017 0x0027 0x0037 0x0047 0x0057 0x0067 0x0077 0x0087 tsersrn (n = 8 to 1) control ds26518 tser source, ports 8 to 1 6.3 id registers bid: board id (offset = 0x0000) bid is read-only with a value of 0xd. xbidh: high nibble extended board id (offset = 0x0002) xbidh is read-only with a value of 0x0. xbidm: middle nibble extended board id (offset = 0x0003) xbidm is read-only with a value of 0x1. xbidl: low nibble extended board id (offset = 0x0004) xbidl is read-only with a value of 0x6. brev: board fab revision (offset = 0x0005) brev is read-only and displays the current fab revision. arev: board assembly revi sion (offset = 0x0006) arev is read-only and displays the current assembly revision. prev: pld revision (offset = 0x0007) prev is read-only and displays the current pld firmware revision. downloaded from: http:///
DS26518DK 9 of 40 6.4 control registers register name: csr register description: ds26518 mclk and refclkio source register offset: 0x0011 bit # 7 6 5 4 3 2 1 0 name rcsrc1 rcsrc0 msrc1 msrc0 default 1 1 0 1 bits 7 and 6: ds26518 refclkio source (rcsrc[1:0]). refclkio connection is defined in table 6-3 . bits 1 and 0: ds26518 mclk source (msrc[1:0]. mclk connection is defined in table 6-4 . table 6-3. refclkio source definition rcsrc[1: 0] refclkio connection 00 drive refclkio with 1.544mhz clock. 01 drive refclkio with 2.048mhz clock. 1x tri-state refclkio. table 6-4. mclk source definition msrc[1:0] mclk connection 00 drive mclk with 1.544mhz clock. 01 drive mclk with 2.048mhz clock. 1x tri-state mclk. downloaded from: http:///
DS26518DK 10 of 40 register name: sysclk_tr register description: ds26518 tsysclk and rsysclk source register offset: 0x0012, 0x0022, 0x0032, 0x0042, 0x0052, 0x0062, 0x0072, 0x0082 bit # 7 6 5 4 3 2 1 0 name rt rs1 rs0 tt ts1 ts0 default 0 1 0 0 0 1 bits 7 to 5: ds26518 port 4 r sysclk source (rt, rs[1:0]). the source for rsysclk is defined as shown in table 6-5 . bits 2 to 0: ds26518 port 1 tsysclk source (tt, ts[1:0]). the source for tsysclk is defined as shown in table 6-6 . table 6-5. rsyscl k source definition rt, rs[1:0] rsysc lk connection 1xx tri-state rsysclk. 000 drive rsysclk with 1.544mhz clock. 001 drive rsysclk with 2.048mhz clock. 010 drive rsysclk with 8.192mhz clock. 011 drive rsysclk with ds26518 port bpclk. table 6-6. tsyscl k source definition tt, ts[1:0] tsysclk connection 1xx tri-state tsysclk. 000 drive tsysclk with 1.544mhz clock. 001 drive tsysclk with 2.048mhz clock. 010 drive tsysclk with 8.192mhz clock. 011 drive tsysclk with ds26518 port bpclk. downloaded from: http:///
DS26518DK 11 of 40 register name: synctss register description: ds26518 tssync source register offset: 0x0013 bit # 7 6 5 4 3 2 1 0 name tsrc3 tsrc2 tsrc1 tsrc0 default 0 0 0 0 bit 3 to 0: ds26518 tssync source select (tsrc[3:0]). the source for tssync is defined in table 6-7 . table 6-7. tssync source definition tsrc[3:0] tssync source definition 0000 not using transmit-side elasti c store, tri-state fpga pin connected to tssync (weak pulldown). 0001 drive tssync with rsync1. 0010 drive tssync with rsync2. 0011 drive tssync with rsync3. 0100 drive tssync with rsync4. 0101 drive tssync with rsync5. 0110 drive tssync with rsync6. 0111 drive tssync with rsync7. 1000 drive tssync with rsync8. note: when driving tssync with rsyncx, the correspondi ng ds26518 port should be configured such that rsyncx is an output (riocr.2 = 0). downloaded from: http:///
DS26518DK 12 of 40 register name: tcsrn (n = 8 to 1) register description: ds26518 tclk source ports 8C1 register offset: 0x0014, 0x0024, 0x0034, 0x0044, 0x0054, 0x0064, 0x0074, 0x0084 bit # 7 6 5 4 3 2 1 0 name tds3 tds2 tds1 tds0 default see note see note see note see note bits 3 to 0: ds26518 port 1 tclk source (tds[3:0]). the source for tclkx is shown in table 6-8 . table 6-8. tclkx source definition tds[3:0] tclkx source definition 0000 tri-state tclkx. 0001 drive tclkx with rclk1. 0010 drive tclkx with rclk2. 0011 drive tclkx with rclk3. 0100 drive tclkx with rclk4. 0101 drive tclkx with rclk5. 0110 drive tclkx with rclk6. 0111 drive tclkx with rclk7. 1000 drive tclkx with rclk8. 1001 drive tclkx with the 1.544mhz clock. 1010 drive tclkx with the 2.048mhz clock. note: initial values are such that tclk1 rclk1, tclk2 rclk2, tclk3 rclk3, tclk4 rclk4, tclk5 rclk5, tclk6 rclk6, tclk7 rclk7, tclk8 rclk8, which corresponds to address 0x14 = 0b0001, address 0x24 = 0b0010, address 0x34 = 0b0011, address 0x44 = 0b0100, address 0x54 = 0b0101, address 0x64 = 0b0110, ad dress 0x74 = 0b0111 and address 0x84 = 0b1000. downloaded from: http:///
DS26518DK 13 of 40 register name: tsyncsn (n = 8 to 1) register description: ds26518 tsync source ports 8 to 1 register offset: 0x0015, 0x0025, 0x0035, 0x0045, 0x0055, 0x0065, 0x0075, 0x0085 bit # 7 6 5 4 3 2 1 0 name tsrc3 tsrc2 tsrc1 tsrc0 default 0 0 0 0 bits 3 to 0: ds26518 port 1 tsync source (tsrc[3:0]). the source for tsyncx is shown in table 6-9 . table 6-9. tsyncx source definition tsrc[3:0] tsyncx source definition 0000 tri-state tsyncx. 0001 drive tsyncx with rsync1. 0010 drive tsyncx with rsync2. 0011 drive tsyncx with rsync3. 0100 drive tsyncx with rsync4. 0101 drive tsyncx with rsync5. 0110 drive tsyncx with rsync6. 0111 drive tsyncx with rsync7. 1000 drive tsyncx with rsync8. note: when driving tsyncx with rsyncx , the corresponding ds26518 port shou ld be configured such that tsyncx is an input (tiocr.2 = 0) and rsyncx is an output (riocr.2 = 0). downloaded from: http:///
DS26518DK 14 of 40 register name: rsyncsrn (n = 8 to 1) register description: ds26518 rsync source select, ports 8 to 1 register offset: 0x0016, 0x0026, 0x0036, 0x0046, 0x0056, 0x0066, 0x0076, 0x0086 bit # 7 6 5 4 3 2 1 0 name rio3 rio2 rio1 rio0 default 0 0 0 0 bits 3 to 0: ds26518 port 1 rsync source (rio[3:0]). the source for rsyncx is shown in table 6-10 . table 6-10. rsyncx source definition rio[3:0] rsyncx source definition 0000 tri-state rsyncx. 0001 drive rsyncx with rsync1. 0010 drive rsyncx with rsync2. 0011 drive rsyncx with rsync3. 0100 drive rsyncx with rsync4. 0101 drive rsyncx with rsync5. 0110 drive rsyncx with rsync6. 0111 drive rsyncx with rsync7. 1000 drive rsyncx with rsync8. note: when driving rsyncy with rsy ncx, the corresponding ds26518 port sh ould be configured such that rsyncx is an output (riocr.2 = 0) an d rsyncy is an input (riocr.2 = 1). downloaded from: http:///
DS26518DK 15 of 40 register name: tsersrn (n = 8 to 1) register description: ds26518 tser source, ports 8 to 1 register offset: 0x0017, 0x0027, 0x0037, 0x0047, 0x0057, 0x0067,0x0077, 0x0087 bit # 7 6 5 4 3 2 1 0 name ts3 ts2 ts1 ts0 default see note see note see note see note bits 3 to 0: ds26518 port 1 tser source (ts[3:0]). the source for tserx is shown in table 6-11 . table 6-11. tserx source definition ts[3:0] tserx source definition 0000 tri-state tserx. 0001 drive tserx with rser1. 0010 drive tserx with rser2. 0011 drive tserx with rser3. 0100 drive tserx with rser4. 0101 drive tserx with rser5. 0110 drive tserx with rser6. 0111 drive tserx with rser7. 1000 drive tserx with rser8. 1001 drive tserx low. note: initial values are such that tser1 rser1, tser2 rser2, tser3 rser3, tser4 rser4, tser5 rser5, tser6 rser6, tser7 rser7, tser8 rser8, which corresponds to address 0x17 = 0b0001, address 0x27 = 0b0010, address 0x37 = 0b0011, address 0x47 = 0b0100, address 0x57 = 0b0101, address 0x67 = 0b0110, ad dress 0x77 = 0b0111 and address 0x87 = 0b1000. downloaded from: http:///
DS26518DK 16 of 40 6.5 fpga control examples external remote loopback (full bandwidth, not just payload) tser tcl k bpcl k tsync rser rcl k bpcl k rsync d s 2651 8 table 6-12. fpga configur ation (port 1, t1 mode) register name setting comment csr 0x01 drive ds26518 mclk with 2.048mhz. tcsr1 0x01 drive tclk1 with rclk1. sysclk_tr 0x00 drive tsysclk with 1.544mhz. tsyncs1 0x01 drive tsync1 with rsync1. synctss 0x01 drive tssync with rsync1. rsyncsrn 0x00 tri-state fpga dr iver pin for ds26518 rsync. tsersr1 0x01 drive ds26518 tser1 with data from rser1. table 6-13. ds26518 partial confi guration (port 1, t1 mode) register name setting comment riocr rsio = 0 rsync is an output. tiocr tsio = 0 tsync is an input. tescr tese = 0 rescr rese = 0 bypass rx and tx elastic stores. tcss1 = 0 tcr3 tcss2 = 0 tclk is driven by tclk pin. downloaded from: http:///
DS26518DK 17 of 40 7. additional information/resources 7.1 ds26518 information for more information about the ds26518, refer to the ds26518 data sheet at www.maxim-ic.com/ds26518 . 7.2 DS26518DK information for more information about the DS26518DK including softw are downloads, refer to the DS26518DK quick view page at www.maxim-ic.com/DS26518DK . 7.3 technical support for additional technical support, go to www.maxim-ic.com/support . downloaded from: http:///
DS26518DK 18 of 40 8. component list designation qty description supplier part c1, c2, c9, c10, cb1, cb3, cb5, cb6, cb7, cb10C cb14, cb16, cb18, cb20C cb23, cb25, cb26, cb29C cb32, cb34, cb49, cb52, cb53, cb54, cb56Ccb63, cb70, cb74, cb75, cb76, cb79, cb80, cb88, cb89, cb100, cb101 49 1 f 10%, 16v ceramic capacitors (1206) panasonic ecj-3yb1c105k c3, c5, c7, c8, cb19, cb35, cb36, cb37, cb47, cb50, cb51, cb55, cb64, cb65, cb66, cb68, cb71, cb102, cb103 19 10 f 20%, 10v ceramic capacitors (1206) panasonic ecj-3yb1a106m c4 1 0.01 f 10%, 50v x7r ceramic capacitor (0603) avx 06035c103kat c6, cb24, cb27, cb38- cb45, cb48, cb67, cb72, cb73, cb77, cb78, cb81- cb87 24 0.1 f 20%, 16v x7r ceramic capacitors (0603) avx 0603yc104mat cb15, cb17 2 22pf 5%, 25v npo ceramic capacitors (0603) avx 06033a220jat cb2, cb28, cb46, cb69 4 68 f 20%, 16v tantalum capacitors (d case) panasonic ecs-t1cd686r cb4, cb33 2 68 f 20%, 16v tantalum capacitors (d case) panasonic ecs-t1cd686r cb8, cb9 2 10pf 5%, 50v ceramic tall- case capacitors (1206) phycomp 1206cg100j9b200 cb90Ccb97 8 0.1 f 10%, 25v ceramic capacitors (1206) panasonic ecj-3vb1e104k cb98, cb99, cb104Ccb109 8 560pf 5%, 50v ceramic ca pacitors (1206) avxz 12065a561jat2a db1 1 1a, 40v schottky diode international rectifier 10bq040 ds1, ds3 2 green smd leds panasonic ln1351c ds2, ds4Cds19 17 red smd leds panasonic ln1251c gnd_tp1Cgnd_tp4, gnd_tpb1 5 standard ground clips keystone 4954 h1Ch4 4 4-40 hardware, 0.50 nylon standoff and nylon hex-nut na 4-40kit4 j1 1 100-mil, 2-7 position jumper na na j2 1 2.1mm/5.5mm powerjack right-angle pcb, closed frame, high current 24v dc at 5a digi-key cp-002ah-nd j3 1 black type b, single, right angle jumper molex na j4 1 db9 right-angle connector (long case) amp 747459-1 j5, j16Cj23 9 100-mil, 2-position jumpers na na j6 1 12-pin, dual-row, vertical connector na na j7 1 terminal strip (10-pin, dual-row, vertical) samtec tsw-105-07-t-d j8Cj15 8 22-pin, dual-row, vertical headers samtec hdr-tsw-111-14-t- d j24Cj39 16 2-pin headers, 0.100 centers, vertical samtec tsw-102-07-t-s jb1, jb2 2 right-angle rj45 8-pi n, 4-port jacks molex 43223-8140 jp1Cjp11 11 100-mil 3-position jumpers na na downloaded from: http:///
DS26518DK 19 of 40 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2007 maxim integrated products the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. designation qty description supplier part r1 1 470 5%, 1/16w resistor (0603) panasonic erj-3geyj471v r2Cr33 32 0 5%, 1/8w resistors (1206) panasonic erj-8geyj0r00v rb1, rb3Crb6, rb10, rb12, rb13, rb16, rb18, rb19, rb21Crb24, rb26, rb27, rb30, rb41 19 10k 5%, 1/16w resistors (0603) panasonic erj-3geyj103v rb2 1 30 5%, 1/16w resistor (0603) panasonic erj-3geyj300v rb7 1 1.0m 5%, 1/16w resistors (0603) panasonic erj-3geyj105v rb8, rb9 2 27 5%, 1/16w resistors (0603) panasonic erj-3geyj270v rb11 1 0 5%, 1/8w resistor (1206) panasonic erj-8geyj0r00v rb14, rb17, rb32 3 1.0k 5%, 1/16w resistors (0603) panasonic erj-3geyj102v rb15 1 1.5k 5%, 1/16w resistor (0603) panasonic erj-3geyj152v rb20, rb29, rb31, rb33, rb36, rb39, rb42, rb43 9 1.0k 5%, 1/16w resistors (0603) panasonic erj-3geyj102v rb25 1 10.0k 1%, 1/16w resistor (0603) panasonic erj-3ekf1002v rb28, rb35, rb44Crb59 18 330 5%, 1/10w resistors (0805) panasonic erj-6geyj331v rb34 1 330 5%, 1/16w resistor (0603) panasonic erj-3geyj331v rb37 1 330 5%, 1/16w resistor (0603) panasonic erj-3geyj331v rb38, rb40 2 0.0 5%, 1/16w resistors (0603) panasonic erj-3gey0r00v rb60Crb75 16 61.9 1%, 1/8w (resistors (1206) panasonic erj-8enf61r9v sw1 1 4-pin single-pole switch panasonic evqpae04m t1, t2 2 smt 32-pin transformers transmit/receive 1:2 and 1:1 pulse tx1475 u1, ub2 2 cypress sram, lab stock na na u2 1 mmc2107 processor motorola mmc2107 u3 1 8-pin max/so 2.5v or adj maxim max1792eua25 u4 1 1mb flash-based configuration mem xilinx xcf01sv020c u5 1 xilinx spartan 2.5v fpga, 256-pin bga xilinx xc2s50-5fg256c u6 1 8-port t1/e1/j1 transceiver, -40 c to +85 c, 256-pin te-csbga dallas semiconductor ds26518 ub1 1 max3233e uart maxim max3233e ub3, ub5 2 linear regulator 1.5w, 3.3v or adj, 1a, 16-pin tssop-ep maxim max1793eue-33 ub4 1 usb uart (usb: 8-bit fi fo), 32-pin lqfp ftd ft245bm ub6 1 linear regulator 1.5w, 1.8v or adj, 1a, 16-pin tssop-ep maxim max1793eue-18 xb1 1 low-profile 8.0mhz crystal ecl ec1-8.000m y1 1 low-profile 6.00mhz crystal pletronics lp49-26-6.00m y2 1 oscillator, crystal clock (3.3v socket) saronix na yb1 1 oscillator, crystal clock (3.3 v, 1.544mhz) saronix nth039a3-1.5440 yb2 1 oscillator (4-pin half-size; 16.348mhz, 50ppm) saronix nch069b3-16.348 9. schematics the schematics are featured in the following pages. downloaded from: http:///
contents / ds26518 octal t1/e1/j1 transceiver design kit 18-21. netlist 13. fgpa configuration / jtag port 15. microprocessor configuration / sram 17. power supply and decoupling 16. usb / rs232 / debug port printed: thu dec 07 08:41:22 2006 DS26518DK01a0 2. ds26518 control 3. ds26518 ports 1-4 4. ds26518 ports 5-8 5. ds26518 bnc / xfrm 1-2 6. ds26518 bnc / xfrm 3-4 7. ds26518 bnc / xfrm 5-6 8. ds26518 bnc / xfrm 7-8 9. fpga (signal mux) 10. ds26518 test points 11. ds26518 test points 12. fgpa address data bus 14. microprocessor 04/17/2006 1. contents steve scully 21 1 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 downloaded from: http:///
/ 04/17/2006 2 DS26518DK01a0 21 steve scully b1 g1 k1 r1 u6 c10 a10 b10 f9 e9 d9 c9 a9 b9 f8 b8 a8 c8 h7 j7 d1 e1 m1 n1 n16 m16 e16 d16 d2 e2 m2 n2 n15 m15 e15 d15 r16 k16 g16 b16 b2 g2 k2 r2 r15 k15 g15 b15 e8 m13 d3 t7 n8 l9 p8 t8 r8 m9 n9 t9 d8 g8 g7 g10 g9 g6 h9 g5 g12 g11 h5 h6 h10 h11 h8 k8 j6 j10 j11 j9 j8 k7 k5 k6 k11 k12 k10 k9 h12 r9 f5 h4 j4 k4 l5 b7 m8 a7 j12 j5 h13 c3 n13 l13 r7 jtms518 jtd518_prom reset_b refclk518 digio_en518 bpclk518 spisel_al_flos1 clko_rlf_ltc1 mclk518 bts518 int518 wr_rw518 rd_ds518 cs518 scanmo518 scanen518 d0_spi_miso tssync518 d1_spi_mosi d2_spi_clk d5_spi_swap d7_spi_cpol d6_spi_cpha txena518 jtdi518_con jtclk518 jtrst518 2 3 1 jp4 2 3 1 jp3 2 3 1 jp2 2 3 1 jp1 dat518_<7..0> 5 d0_spi_miso spi_miso d2_spi_clk 7 spi_sck jmp_3 4 d1_spi_mosi jmp_3 0 spi_mosi spi_ss cs_x1 cs518 11 10 addr518_<12..0> 8 2 12 6 4 3 1 05 9 7 jmp_3 jmp_3 2 1 3 6 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v1_8 v1_8 control ds26518_u dvdd18_1 dvdd18_2 dvdd18_3 reset* refclkio digioen bpclk1 spi_sel/al/rsigf/flos1 clko/rlf/ltc1 mclk bts int* wr*/rw* rd*/ds* cs* scanmode scanen/resref jtdo dvdd33_10 dvdd33_6 dvdd33_8 dvdd33_7 dvdd33_5 dvdd33_4 dvdd33_9 arvdd8 arvdd7 arvdd5 arvdd6 arvdd4 arvdd3 arvdd2 arvdd1 acvdd atvdd8 atvdd7 atvdd6 atvdd5 atvdd4 atvdd3 atvdd2 atvdd1 dvss1 dvss6 dvss5 dvss4 dvss3 dvss2 dvss7 dvss8 dvss9 dvss10 dvss11 dvss12 dvss13 dvss14 arvss1 arvss8 arvss7 arvss6 arvss5 arvss4 arvss3 arvss2 atvss1 atvss2 atvss3 atvss4 atvss5 atvss6 atvss7 atvss8 acvss d<0>/spi_miso tssync a<5> a<1> a<0> a<2> a<3> a<4> a<6> a<7> a<8> a<9> a<10> a<12> d<1>/spi_mosi d<2>/spi_sclk d<3> d<5>/spi_swap d<4> d<7>/spi_cpol d<6>/spi_cpha a<11> jtms txenable jtdi jtclk jtrst dvdd33_1 dvdd18_4 dvdd33_3 dvdd33_2 v3_3 downloaded from: http:///
2 3 4 / / port4 pin p2 port2 pin f2 port1 pin c2 port3 pin l2 3 steve scully 04/17/2006 DS26518DK01a0 21 tsync518_<8..1> tchbk518_<8..1> tsig518_<8..1> tser518_<8..1> tclk518_<8..1> ttip518_<8..1> tring518_<8..1> p6 22 2 2 2 2 2 2 3 4 2 3 4 1 1 33 33 3 1 1 1 33 3 3 3 33 3 3 4 4 4 4 4 44 4 4 4 22 2 2 2 11 1 11 1 1 3 1 1 1 1 1 22 2 44 4 4 4 rring518_<8..1> tring518_<8..1> rtip518_<8..1> ttip518_<8..1> rclk518_<8..1> tclk518_<8..1> rser518_<8..1> tser518_<8..1> rsig518_<8..1> tsig518_<8..1> rm518_<8..1> tsysclk518_<8..1> tsysclk518_<8..1> rsysclk518_<8..1> rsysclk518_<8..1> rchbk518_<8..1> tchbk518_<8..1> rsync518_<8..1> tsync518_<8..1> tsysclk518_<8..1> rsysclk518_<8..1> rsysclk518_<8..1> u6 e4 f4 c4 c2 e5 d4 a4 l12 c1 a5 c5 b3 a3 f6 d5 p13 a1 a2 u6 t5 m4 p2 n6 r5 t6 n3 p1 p7 l8 t3 r3 n7 r6 m7 p3 t2 t1 u6 l6 l4 p4 l2 n4 m5 n5 m3 l1 l7 p5 k3 j3 r4 t4 m6 l3 j2 j1 u6 b5 g4 c6 f2 d6 e6 b6 e3 f1 c7 d7 g3 h3 e7 f7 f3 h2 h1 b4 a6 tsysclk518_<8..1> rring518_<8..1> rtip518_<8..1> rclk518_<8..1> rser518_<8..1> rsig518_<8..1> rm518_<8..1> rchbk518_<8..1> rsync518_<8..1> tring518_<8..1> ttip518_<8..1> tclk518_<8..1> tser518_<8..1> tsig518_<8..1> tchbk518_<8..1> tsync518_<8..1> rchbk518_<8..1> rring518_<8..1> rtip518_<8..1> rm518_<8..1> rser518_<8..1> rsig518_<8..1> rclk518_<8..1> rsync518_<8..1> tring518_<8..1> ttip518_<8..1> tclk518_<8..1> tser518_<8..1> tsig518_<8..1> tchbk518_<8..1> tsync518_<8..1> rring518_<8..1> rtip518_<8..1> rclk518_<8..1> rser518_<8..1> rsig518_<8..1> rm518_<8..1> rchbk518_<8..1> rsync518_<8..1> page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 port ds26518_u rring rtip tsync/tssyncio rsync rchblk_clk rsysclk/rlf/ltc tchblk_clk tringa tringb ttipa ttipb tser tclk tsig rclk rser rsig rm_rfsync tsysclk/al/rsigf/flos port ds26518_u rring rtip tsync/tssyncio rsync rchblk_clk rsysclk/rlf/ltc tchblk_clk tringa tringb ttipa ttipb tser tclk tsig rclk rser rsig rm_rfsync tsysclk/al/rsigf/flos port ds26518_u rring rtip tsync/tssyncio rsync rchblk_clk rsysclk/rlf/ltc tchblk_clk tringa tringb ttipa ttipb tser tclk tsig rclk rser rsig rm_rfsync tsysclk/al/rsigf/flos port 1 ds26518_u rm_rfsync1 tsig1 tser1 tclk1 ttipb1 ttipa1 tringb1 tringa1 rsig1 rser1 rclk1 rring1 rsysclk1 rchblk_clk1 rsync1 tchblk_clk1 tsync/tssyncio1 tsysclk1 rtip1 downloaded from: http:///
port5 pin p15 / port6 pin l15 port8 pin c15 port7 pin f15 4 steve scully 04/17/2006 DS26518DK01a0 21 rring518_<8..1> rclk518_<8..1> j16 j15 l14 t12 r12 l11 j14 k14 n11 p11 l16 m14 p12 r13 m12 l15 n12 j13 t13 u6 t15 t16 p14 n10 t10 m10 t14 r14 l10 p9 p16 n14 r10 r11 m11 p15 p10 k13 t11 u6 h15 h16 f14 b11 a11 f10 h14 g14 e10 d10 f16 e14 c11 a12 b12 f15 d11 f13 c12 u6 a16 a15 c14 a13 c13 d12 b14 a14 b13 e11 c16 d14 d13 f12 f11 c15 e12 e13 g13 u6 tsync518_<8..1> rsync518_<8..1> tsync518_<8..1> rsync518_<8..1> tchbk518_<8..1> rchbk518_<8..1> tchbk518_<8..1> rchbk518_<8..1> rsysclk518_<8..1> rsysclk518_<8..1> tsysclk518_<8..1> tsysclk518_<8..1> rm518_<8..1> rm518_<8..1> tsig518_<8..1> rsig518_<8..1> tsig518_<8..1> rsig518_<8..1> tser518_<8..1> rser518_<8..1> tser518_<8..1> rser518_<8..1> tclk518_<8..1> rclk518_<8..1> tclk518_<8..1> rclk518_<8..1> ttip518_<8..1> ttip518_<8..1> rtip518_<8..1> rtip518_<8..1> tring518_<8..1> rring518_<8..1> tring518_<8..1> rring518_<8..1> tsync518_<8..1> rsync518_<8..1> tsync518_<8..1> rsync518_<8..1> tchbk518_<8..1> rchbk518_<8..1> tchbk518_<8..1> rchbk518_<8..1> rsysclk518_<8..1> rsysclk518_<8..1> tsysclk518_<8..1> tsysclk518_<8..1> rm518_<8..1> rm518_<8..1> tsig518_<8..1> rsig518_<8..1> tsig518_<8..1> rsig518_<8..1> tser518_<8..1> rser518_<8..1> tser518_<8..1> rser518_<8..1> tclk518_<8..1> rclk518_<8..1> tclk518_<8..1> ttip518_<8..1> ttip518_<8..1> rtip518_<8..1> rtip518_<8..1> tring518_<8..1> rring518_<8..1> tring518_<8..1> 8 88 8 8 8 8 88 88 8 8 8 8 77 7 7 7 7 7 7 77 7 7 7 7 7 7 7 55 5 5 5 5 5 55 5 5 5 5 66 6 6 66 6 6 66 6 5 5 5 6 6 66 6 6 5 8 8 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 port ds26518_u rring rtip tsync/tssyncio rsync rchblk_clk rsysclk/rlf/ltc tchblk_clk tringa tringb ttipa ttipb tser tclk tsig rclk rser rsig rm_rfsync tsysclk/al/rsigf/flos port ds26518_u rring rtip tsync/tssyncio rsync rchblk_clk rsysclk/rlf/ltc tchblk_clk tringa tringb ttipa ttipb tser tclk tsig rclk rser rsig rm_rfsync tsysclk/al/rsigf/flos port ds26518_u rring rtip tsync/tssyncio rsync rchblk_clk rsysclk/rlf/ltc tchblk_clk tringa tringb ttipa ttipb tser tclk tsig rclk rser rsig rm_rfsync tsysclk/al/rsigf/flos port ds26518_u rring rtip tsync/tssyncio rsync rchblk_clk rsysclk/rlf/ltc tchblk_clk tringa tringb ttipa ttipb tser tclk tsig rclk rser rsig rm_rfsync tsysclk/al/rsigf/flos downloaded from: http:///
/ 04/17/2006 DS26518DK01a0 21 5 steve scully 1 2 j17 2 1 rb74 2 1 cb97 2 1 rb75 1 2 r10 1 2 r11 13 20 14 19 t1 1 2 r26 1 2 r27 2 1 cb107 17 16 18 15 t1 d8 d7 d6 d5 d4 d3 d2 d1 jb2 1 2 j25 1 2 j16 2 1 rb72 2 1 cb96 2 1 rb73 1 2 r12 1 2 r13 11 22 12 21 t1 1 2 j24 1 2 r3 1 2 r2 2 1 cb98 23 10 24 9 t1 c8 c7 c6 c5 c4 c3 c2 c1 jb2 1 2 j27 1 2 j26 rring518_<8..1> rring518_<8..1> rtip518_<8..1> rtip518_<8..1> tring518_<8..1> tring518_<8..1> ttip518_<8..1> ttip518_<8..1> 0 0.1uf disinvtx2 disinvrx2 disinvtx1 rj45_4port 560pf 00 22 00 61.9 0.1uf 22 560pf 1 0 1 0 61.9 11 61.9 61.9 0 disinvrx1 rj45_4port page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 1:2 6 5 rj45 7 4 3 2 1 8 g s 1:1 1:2 6 5 rj45 7 4 3 2 1 8 g s 1:1 g s g s downloaded from: http:///
/ 6 steve scully 04/17/2006 DS26518DK01a0 21 tring518_<8..1> 1 2 j19 1 2 j18 2 1 rb71 2 1 cb95 2 1 rb70 1 2 r15 1 2 r14 6 27 5 28 t1 1 2 r7 1 2 r6 2 1 cb104 25 8 26 7 t1 1 2 j29 b8 b7 b6 b5 b4 b3 b2 b1 jb2 1 2 j28 2 1 rb69 2 1 cb94 2 1 rb68 1 2 r17 1 2 r16 4 29 3 30 t1 1 2 r29 1 2 r28 2 1 cb106 32 1 31 2 t1 1 2 j31 a8 a7 a6 a5 a4 a3 a2 a1 jb2 1 2 j30 rring518_<8..1> rring518_<8..1> rtip518_<8..1> rtip518_<8..1> tring518_<8..1> ttip518_<8..1> ttip518_<8..1> disinvtx4 disinvtx3 0 disinvrx3 rj45_4port 560pf 00 44 0 61.9 0.1uf 44 61.9 560pf 0 3 0 3 00 61.9 0.1uf 33 61.9 rj45_4port disinvrx4 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 1:1 1:2 g s 6 5 rj45 7 4 3 2 1 8 g s 1:1 1:2 g s 6 5 rj45 7 4 3 2 1 8 g s downloaded from: http:///
/ steve scully 21 7 DS26518DK01a0 04/17/2006 tring518_<8..1> 1 2 j21 1 2 j20 1 2 rb67 2 1 cb93 2 1 rb66 1 2 r19 1 2 r18 1 2 r30 1 2 r31 14 19 13 20 t2 d8 d7 d6 d5 d4 d3 d2 d1 jb1 1 2 j33 2 1 cb109 17 16 18 15 t2 1 2 j32 1 2 rb64 2 1 cb92 1 2 rb65 1 2 r20 1 2 r21 1 2 r4 1 2 r5 11 22 12 21 t2 c8 c7 c6 c5 c4 c3 c2 c1 jb1 1 2 j35 2 1 cb99 24 9 23 10 t2 1 2 j34 rring518_<8..1> rring518_<8..1> rtip518_<8..1> rtip518_<8..1> tring518_<8..1> ttip518_<8..1> ttip518_<8..1> 0.1uf disinvtx6 disinvtx5 disinvrx5 560pf rj45_4port 00 66 00 66 61.9 61.9 0 5 0 5 00 55 61.9 0.1uf 61.9 rj45_4port 560pf disinvrx6 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 1:1 6 5 rj45 7 4 3 2 1 8 g s 1:2 1:1 6 5 rj45 7 4 3 2 1 8 g s 1:2 g s g s downloaded from: http:///
/ steve scully 04/17/2006 8 21 DS26518DK01a0 1 2 j23 1 2 j22 1 2 cb91 2 1 rb63 2 1 rb62 1 2 r23 1 2 r22 6 27 5 28 t2 b8 b7 b6 b5 b4 b3 b2 b1 jb1 1 2 j37 1 2 r8 1 2 r9 2 1 cb105 26 7 25 8 t2 1 2 j36 2 1 cb90 2 1 rb61 2 1 rb60 1 2 r25 1 2 r24 4 29 3 30 t2 a8 a7 a6 a5 a4 a3 a2 a1 jb1 1 2 j39 1 2 r33 1 2 r32 2 1 cb108 32 1 31 2 t2 1 2 j38 rring518_<8..1> rring518_<8..1> rtip518_<8..1> rtip518_<8..1> tring518_<8..1> tring518_<8..1> ttip518_<8..1> ttip518_<8..1> rj45_4port 0.1uf 61.9 61.9 7 7 0 0 7 7 0 0 560pf 0.1uf 61.9 61.9 8 8 0 0 rj45_4port 8 8 0 0 560pf disinvrx7 disinvtx7 disinvtx8 disinvrx8 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 1:1 6 5 rj45 7 4 3 2 1 8 g s 1:2 g s 1:2 1:1 6 5 rj45 7 4 3 2 1 8 g s g s downloaded from: http:///
(low for normal operation) (low for normal operation) (high for normal operation) (high for normal operation) (high for moto mode) (low for parallel port) / 1% tolerance steve scully 9 04/17/2006 21 DS26518DK01a0 1.0k 1.0k 1.0k spisel_al_flos1 3 rser518_<8..1> tssync518 tsync518_<8..1> bpclk518 refclk518 mclk518 clko_rlf_ltc1 tser518_<8..1> bts518 tclk518_<8..1> rclk518_<8..1> rsysclk518_<8..1> 1 6 4 d7_spi_cpol d6_spi_cpha d5_spi_swap 1.0k 1.0k 1.0k 1 2 3 4 5 6 7 1 8 2 3 4 5 6 8 7 8 7 65 4 1 1 2 4 7 5 6 1 8 2 3 1 2 3 45 6 54 6 7 8 7 8 7 54 2 3 1 2 3 5 6 7 8 1.0k digio_en518 u5 n8 r8 d1 r13 n1 l2 r6 p13 f1 p6 t7 k2 m4 g1 m3 h4 l3 p5 g5 r7 m10 e3 k1 n5 n6 f2 t9 h1 k3 f3 m6 e4 p7 g2 n7 f4 t8 n12 l5 h2 g3 n2 m7 j2 r1 p12 r12 j1 n10 p11 g4 p10 t13 f5 t10 p1 t4 r5 j4 p9 k5 m2 c1 t3 r9 j3 n11 t2 n9 t6 r11 a2 r10 m1 m11 b1 t11 d2 t5 c2 p8 e1 l1 t12 l4 e2 h3 jp9 1 3 jp5 1 3 2 jp6 1 3 2 rb29 1 2 rb31 1 2 rb33 1 2 jp7 1 3 2 jp8 1 3 2 rb36 1 2 rb20 1 2 rb39 1 2 jp10 1 3 2 1 2 rb43 1 2 jp11 1 3 2 2 1.0k rb42 scanen518 scanmo518 t14 8 tsysclk518_<8..1> rsync518_<8..1> 3 2 k4 txena518 rb25 10.0k page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 bank 5 bank 7 xc2s50_bga bank 6 bank 4 io11_7 io19_5 io4_6\vref io2_4 io5_5 io1_6\trdy io2_6 io3_6 io5_6 io6_6 io7_6 io8_6 io9_6 io10_6\vref io11_6 io12_6 io13_6 io14_6 io15_6 io16_6 io17_6 io3_4\vref io1_4 io1_5 gck1 io23_7 io22_7 io21_7 io20_7 io19_7 io18_7 io17_7 io16_7 io15_7 io14_7 io13_7 io12_7\irdy io10_7 io9_7\vref io8_7 io7_7 io6_7 io5_7 io4_7 io3_7\vref io2_7 io1_7 io23_6 io22_6 io21_6 io20_6 io19_6 io18_6 io18_5 io17_5 io16_5 io15_5 io14_5 io13_5 io12_5 io11_5 io10_5 io9_5 io8_5\vref io7_5 io6_5 io4_5 io3_5 io2_5\vref io22_4 io21_4 io20_4 io19_4 io18_4 io17_4 io16_4 io15_4 io14_4 io13_4 io12_4 io11_4 io10_4 io9_4\vref io8_4 io7_4 io6_4 io5_4 io4_4 gck0 downloaded from: http:///
/ 330 ohm 330 ohm rlos leds rlf leds (rlos and rlf are only valid in ds26528 mode) 10 21 04/17/2006 steve scully DS26518DK01a0 j6 19 tsig518_<8..1> rm518_<8..1> 12 11 10 9 8 7 6 5 4 3 2 1 20 19 18 17 22 21 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j9 20 19 18 17 22 21 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j10 20 19 18 17 22 21 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j11 20 18 17 22 21 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j8 2 2 1 2 rb45 2 2 2 1 rb51 1 2 rb53 2 2 2 1 2 rb57 1 2 rb58 1 2 rb54 2 1 2 rb48 2 1 rb46 2 1 rb44 2 2 2 2 1 rb50 2 1 rb52 2 2 2 1 rb56 2 1 rb59 2 1 rb55 2 2 1 2 rb49 2 1 rb47 spisel_al_flos1 clko_rlf_ltc1 tsysclk518_<8..1> 1 tsync518_<8..1> rsync518_<8..1> tser518_<8..1> rser518_<8..1> tclk518_<8..1> rclk518_<8..1> led_rlos518_<8..1> rsysclk518_<8..1> mclk518 refclk518 bpclk518 tssync518 led_rlf518_<8..1> led_rlos518_<8..1> led_rlf518_<8..1> rm518_<8..1> led_rlf518_<8..1> rsysclk518_<8..1> tsig518_<8..1> rsysclk518_<8..1> rsig518_<8..1> rsig518_<8..1> led_rlos518_<8..1> tchbk518_<8..1> led_rlos518_<8..1> tchbk518_<8..1> tsysclk518_<8..1> rchbk518_<8..1> tsysclk518_<8..1> rchbk518_<8..1> tsync518_<8..1> tsync518_<8..1> rsync518_<8..1> rsync518_<8..1> tser518_<8..1> tser518_<8..1> rser518_<8..1> rser518_<8..1> tclk518_<8..1> tclk518_<8..1> rclk518_<8..1> rclk518_<8..1> rm518_<8..1> led_rlf518_<8..1> rm518_<8..1> tsig518_<8..1> rsysclk518_<8..1> tsig518_<8..1> rsig518_<8..1> rsig518_<8..1> tchbk518_<8..1> led_rlos518_<8..1> tchbk518_<8..1> rchbk518_<8..1> tsysclk518_<8..1> rchbk518_<8..1> tsync518_<8..1> rsync518_<8..1> led_rlf518_<8..1> tser518_<8..1> rser518_<8..1> tclk518_<8..1> rclk518_<8..1> 86 7 54 3 1 2 86 7 54 3 2 1 1 1 33 3 3 3 33 3 3 3 3 44 4 44 4 4 4 4 4 4 11 11 1 1 1 22 2 2 2 2 2 2 22 2 11 1 1 33 3 3 44 4 4 1 22 2 2 2 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 con12p 13 11 4 17 7 26 9 15 5 8 1 3 10 12 14 16 18 20 19 22 21 conn_22p 13 11 4 17 7 26 9 15 5 8 1 3 10 12 14 16 18 20 19 22 21 conn_22p 13 11 4 17 7 26 9 15 5 8 1 3 10 12 14 16 18 20 19 22 21 conn_22p 13 11 4 17 7 26 9 15 5 8 1 3 10 12 14 16 18 20 19 22 21 conn_22p downloaded from: http:///
/ 11 17 DS26518DK01a0 04/17/2006 steve scully 20 19 18 17 22 21 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j15 20 19 18 17 22 21 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j12 20 19 18 17 22 21 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j13 20 19 18 17 22 21 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j14 tsysclk518_<8..1> led_rlos518_<8..1> rclk518_<8..1> tsysclk518_<8..1> led_rlos518_<8..1> rm518_<8..1> led_rlos518_<8..1> tsysclk518_<8..1> led_rlf518_<8..1> led_rlf518_<8..1> rm518_<8..1> rsysclk518_<8..1> tsig518_<8..1> rsysclk518_<8..1> tsig518_<8..1> rsig518_<8..1> rsig518_<8..1> tchbk518_<8..1> tchbk518_<8..1> rchbk518_<8..1> rchbk518_<8..1> tsync518_<8..1> tsync518_<8..1> rsync518_<8..1> rsync518_<8..1> tser518_<8..1> tser518_<8..1> rser518_<8..1> rser518_<8..1> tclk518_<8..1> tclk518_<8..1> rclk518_<8..1> led_rlf518_<8..1> rm518_<8..1> led_rlf518_<8..1> rm518_<8..1> rsysclk518_<8..1> tsig518_<8..1> rsysclk518_<8..1> tsig518_<8..1> rsig518_<8..1> rsig518_<8..1> tchbk518_<8..1> led_rlos518_<8..1> tchbk518_<8..1> rchbk518_<8..1> tsysclk518_<8..1> rchbk518_<8..1> tsync518_<8..1> tsync518_<8..1> rsync518_<8..1> rsync518_<8..1> tser518_<8..1> tser518_<8..1> rser518_<8..1> rser518_<8..1> tclk518_<8..1> tclk518_<8..1> rclk518_<8..1> rclk518_<8..1> 88 8 77 7 7 55 5 5 6 6 6 6 6 6 8 77 7 7 7 7 7 7 7 77 88 8 8 8 8 8 8 8 8 55 5 5 5 5 5 5 5 5 5 66 6 6 6 66 66 8 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 13 11 4 17 7 26 9 15 5 8 1 3 10 12 14 16 18 20 19 22 21 conn_22p 13 11 4 17 7 26 9 15 5 8 1 3 10 12 14 16 18 20 19 22 21 conn_22p 13 11 4 17 7 26 9 15 5 8 1 3 10 12 14 16 18 20 19 22 21 conn_22p 13 11 4 17 7 26 9 15 5 8 1 3 10 12 14 16 18 20 19 22 21 conn_22p downloaded from: http:///
/ DS26518DK01a0 12 04/17/2006 21 steve scully socket 1.544mhz_3.3v 16.348mhz k15 h16 dat518_<7..0> 8 1 5 4 y2 2 1 rb35 2 1 ds2 8 1 5 4 yb2 8 1 5 4 yb1 2 1 ds1 2 1 rb28 d16 k14 b9 d5 m16 e10 c10 c5 n16 e16 a11 b4 f16 f15 b11 b5 a6 f12 e11 a5 l14 h13 c11 b3 t15 g16 a14 a4 n14 a7 c13 b7 b16 g12 c16 h14 f14 d10 j13 c6 h15 b6 k12 r16 n15 b13 a3 g13 d9 g15 e6 e14 j14 b10 l12 a9 l16 a12 k13 e15 c8 d11 p16 a10 d8 a13 m15 d7 c7 b12 l13 j15 c15 d12 m14 g14 d14 c12 d6 j16 l15 a8 e7 k16 f13 e13 m13 b8 c9 u5 oscsocket oscsocket osc16348 7 pdata<31..16> 31 30 12 cs_x1 pwren#usb rxf#usb txe#usb wrusb paddr<15..0> pdata<31..16> eb1_m oe_m rw_m rd#usb si_wuusb cpuclk_out x_init cfg_din eb0_m cs2_m cs1_m osc1544 2 3 4 1 0 5 6 7 8 9 10 11 12 13 14 24 25 26 27 28 29 16 17 18 19 20 21 22 23 0 1 2 3 4 5 6 red 0 1 2 3 4 5 6 7 8 9 10 11 green addr518_<12..0> int518_led int518 wr_rw518 rd_ds518 int518_led osc16348 osc1544 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 vcc 1 osc gnd out v3_3 vcc 1 osc gnd out vcc 1 osc gnd out v3_3 v3_3 v3_3 xc2s50_bga bank 2 bank 0 bank 3 bank 1 io10_1 io9_1\vref io1_1\cs* io2_1\write* io3_1 io4_1\vref io5_1 io4_0 io3_0 io2_0\vref gck3 io15_3 io14_3 io23_3 io22_3 io21_3 io20_3 io19_3 io18_3 io17_3 io16_3 io13_3\trdy io12_3 io11_3\d4 io10_3\vref io9_3 io8_3\d5 io7_3\d6 io6_3 io5_3 io4_3\vref io3_3 io2_3\d7 io1_3\init* io24_2 io23_2 io22_2 io21_2 io20_2 io19_2 io18_2 io17_2 io16_2 io15_2 io14_2 io13_2\(dout,busy) io12_2\(din,d0) io11_2 io10_2\vref io9_2 io8_2 io7_2\d1 io6_2\d2 io5_2 io4_2 io3_2\d3 io2_2\vref io2_1\irdy io22_1 io21_1 io20_1 io19_1 io18_1 io17_1 io16_1 io15_1 io14_1 io13_1 io12_1 io11_1 io8_1 io7_1 io6_1 gck2 io20_0 io19_0 io18_0 io17_0 io16_0 io15_0 io14_0 io13_0 io12_0 io11_0 io10_0 io9_0 io8_0 io7_0\vref io6_0 io5_0 io1_0 downloaded from: http:///
jtag configuration jtms518 jtms tdi jtclk jtclk518 ds26518 tdo tdi flash config tdo tdi fpga tdo / DS26518DK01a0 04/17/2006 steve scully 13 21 jtd_prom2spart a15 1 330 jtms518 jtclk518 reset_b 10k xrst done jtclk jtms cclk jtd_prom2spart cfg_din x_init 10k .1uf .1uf .1uf .1uf 1uf 1uf 1uf 10uf 1uf 1uf 1uf jtdo_spart2con jtclk jtms jtdi518_con jtrst518 jtd518_prom rb34 2 u4 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 rb41 2 1 rb30 2 1 j7 1 2 3 4 5 6 7 8 9 10 cb44 2 1 cb43 2 1 cb40 2 1 cb39 2 1 cb30 1 2 cb25 2 1 cb34 1 2 cb47 1 2 u3 1 6 2 3 7 8 4 5 cb74 1 2 cb63 2 1 cb62 2 1 jtd518_prom l9 j12 j11 h12 h11 f9 e9 f8 h6 h5 j6 j5 m8 l8 m9 e8 n4 m12 m5 e12 e5 d13 d4 c14 p14 p3 n13 c3 d3 b14 c4 p15 r4 p4 r3 p2 n3 g6 f11 f10 f7 f6 b15 t16 t1 r15 r2 l11 l10 l7 b2 l6 k11 k10 k9 k8 k7 k6 j10 j9 j8 a16 j7 h10 h9 h8 h7 g11 g10 g9 g8 g7 a1 r14 d15 u5 jtms jtclk jtdo_spart2con cclk done xrst page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 xc2s50_bga control vcco8 vccint5 vccint1 vccint9 program* gnd36 gnd35 gnd34 gnd33 gnd32 gnd31 gnd30 gnd28 gnd27 gnd26 gnd25 gnd24 gnd23 gnd21 gnd20 gnd19 gnd18 gnd16 gnd15 gnd13 gnd12 gnd11 gnd10 gnd9 gnd8 gnd7 vcco3 vcco2 gnd1 gnd2 gnd3 gnd4 gnd5 gnd6 gnd14 gnd17 gnd22 gnd29 nc1 nc2 m2 m1 m0 done cclk tdo tck tdi tms vccint12 vccint11 vccint10 vccint8 vccint7 vccint6 vccint4 vccint3 vccint2 vcco16 vcco15 vcco14 vcco13 vcco12 vcco11 vcco10 vcco9 vcco7 vcco6 vcco5 vcco4 vcco1 v3_3 v2_5 v3_3 max1792 in out set gnd out in shdn rst v2_5 tdi tdo tck rst tms conn_jtag gnd vcc v3_3 v2_5 ce* tck tms clk d0 dnc1 oe/rst* dnc2 tdi cf* xilinx_xcf01s vccj vcco vccint tdo dnc3 gnd dnc6 ceo* dnc5 dnc4 v3_3 downloaded from: http:///
/ steve scully 04/17/2006 DS26518DK01a0 14 21 92 126 73 114 140 127 76 64 44 32 18 8 112 113 87 123 103 74 115 141 129 77 65 45 33 19 9 102 99 97 59 95 37 38 39 40 41 42 144 1 43 2 3 45 7 10 12 15 16 17 46 20 21 22 25 27 30 31 34 35 36 48 51 13 14 23 24 26 28 29 116 117 119 47 121 122 131 132 134 136 137 139 6 11 49 50 u2 80 124 66 69 142 138 63 135 133 130 67 78 94 93 68 70 120 118 104 105 106 107 108 109 110 111 90 91 89 88 84 82 79 75 72 71 52 53 54 55 56 57 58 61 125 96 98 100 101 143 60 62 81 83 85 86 128 u2 2 1 rb11 int518 spi_mosi spi_miso xtal osc_mcu once_tclk once_trst_b vddsyn 0.0 once_de_b spi_ss spi_sck once_tms rcon oe_m flash_vpp rw_m 10 sci1_in sci2_out test pqb0 pqa4 pqa3 pqa0 pqa1 once_tdi once_tdo tim_16h_8l pqb1 pqb2 pqb3 eb0_m eb1_m cs1_m cs2_m cpuclk_out reset_b cs0 sci2_in sci1_out 8 19 paddr<22..0> 22 21 20 19 18 17 16 15 14 13 12 11 10 98 7 65 4 3 2 1 31 29 28 27 26 25 24 23 20 18 15 16 14 13 12 11 0 1 2 3 4 5 6 7 9 0 pdata<31..0> 22 21 gnd 30 17 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 mmc2107 port ta* shs* oe* vrh vstby tea* vddh vddf vdda vpp vdd6 vdd7 vdd8 vddsyn vdd3 vdd5 rw vrl a8 d31 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a7 a6 a5 a4 a3 a2 a1 a0 vss1 vss2 vss3 vss4 vss5 vss6 vss7 vss8 vsssyn vssf vssa d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 vdd2 vdd1 vdd4 mmc2107 control rxd1 int7* txd2 icoc10 test int1* icoc13 icoc12 icoc11 icoc21 icoc20 icoc23 icoc22 extal tclk trst* ss* pqb0 pqa4 pqa3 pqa0 pqa1 cs3* tc1 tdi tdo cse1 eb3* int6* pqb1 pqb2 pqb3 eb0* eb1* eb2* tc2 cse0 cs1* cs2* de* sck rstout* clkout reset* cs0* tms int0* yc0 mosi miso xtal int3* int2* int5* int4 rxd2 txd1 v3_3 downloaded from: http:///
reset configuration reset and chip configuration boot / full drive xtal w/ pll internal intern/extern flash enable master mode and is hand soldered to sw1.2+sw1.3 note: cb_rwk1 is a rework component 15 21 DS26518DK01a0 04/17/2006 steve scully osc_mcu rb32 10uf 1 cy62128v eb0_m oe_m paddr<17..1> cs0 eb1_m oe_m pdata<23..16> 8 7 10 9 11 12 13 14 15 16 cy62128v 17 65 4 3 2 1 17 16 18 19 20 22 21 23 1.0k paddr<17..1> cs0 pdata<31..24> 10 9 11 13 12 14 15 16 17 8 7 65 4 3 2 1 25 24 27 26 28 30 29 31 tim_16h_8l 1.0k 10k 10k 10k 10k 10k 10k 10k 10k 1.0m 10k 8.0mhz 10pf 10pf xtal rcon pdata<26> pdata<17> pdata<16> pdata<21> pdata<23> pdata<22> pdata<28> pdata<19> pdata<18> 10k 10k rb18 rb23 rb21 rb26 rb10 rb19 rb24 rb22 rb27 rb7 1 2 rb16 xb1 2 1 3 cb8 1 2 cb9 1 2 rb17 j5 2 1 u1 25 2 23 10 28 12 31 11 9 3 4 5 6 7 8 27 26 22 30 16 13 14 15 17 18 19 20 21 1 24 32 29 ub2 2 25 10 28 11 31 12 9 3 4 5 6 7 8 26 23 22 30 16 13 17 20 21 19 14 18 15 1 24 32 29 rb5 4 27 2 reset_b cb_rwk1 sw1 flash_vpp page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 cy62128v ce1* ce2 a7 a6 a5 a4 a3 a2 a1 a0 n_c we* oe* gnd vcc a16 a15 a14 a13 a12 a11 a10 a9 a8 io0 io1 io2 io3 io4 io5 io6 io7 v3_3 v3_3 v3_3 v5_0 cy62128v ce1* ce2 a7 a6 a5 a4 a3 a2 a1 a0 n_c we* oe* gnd vcc a16 a15 a14 a13 a12 a11 a10 a9 a8 io0 io1 io2 io3 io4 io5 io6 io7 v3_3 v3_3 downloaded from: http:///
align key / mmc2107 tms, tck, de and tdi have int pullup ds26528dk02a0 19 16 08/15/2005 steve scully 9 8 7 6 5 4 3 2 1 j4 2 1 rb6 2 1 rb13 2 1 rb12 9 17 12 11 19 3 7 4 1 20 68 2 18 5 10 16 15 14 13 ub1 2 1 cb15 1 2 y1 1 2 rb2 5 4 3 2 1 j3 2 1 rb1 2 1 rb9 2 1 rb8 2 1 cb17 1 2 rb15 1 2 c4 1 2 c6 2 1 r1 28 27 13 26 3 7 8 12 16 25 31 10 11 24 23 5 18 4 15 14 17 9 1 2 32 21 20 19 22 30 29 6 ub4 1 2 rb4 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j1 2 1 rb3 22pf dat518_<7..0> once_tdo reset_b once_tclk gnd once_tdi once_trst_b rxf#usb txe#usb wrusb rd#usb prt1_in prt1_out prt1_out sci1_in sci1_out prt1_in si_wuusb pwren#usb once_de_b once_tms 10k 10k 10k 22pf 6.00mhz 30 usb 10k 27 27 1.5k .01uf .1uf 470 7 6 5 4 3 2 1 0 10k con14p 10k page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 con14p conn_db9p h g f c a b de j v3_3 v3_3 max3233e invalid* t2in t2out gnd v- c2- c2+ c1- c1+ v+2 v+1 forceoff* vcc t1out r1out forceon t1in r1in r2out r2in v3_3 gnd dat- vdd dat+ usb ft245bm_u si_wu rxf# pwren# 3v3out rd# xtout xtin d6 usbdm usbdp vcc1 reset# eecs eesk eedata test gnd1 gnd2 agnd vccio vcc2 avcc wr txe# d1 d0 d4 d3 d2 d5 d7 rstout# v3_3 v5_0 v3_3 downloaded from: http:///
1.8v 1% regulator 3.3v 1% regulator to ensure load sharing between the 3.3v 1% regulators be long enough to build 0.06 ohm of resistance 3.3v 1% regulator trace geometry for this is: 1 inch long, 10 mil wide, 1 oz coppe r traces between regulator output and v3.3 should 17 / 21 ds26528dk02a0 08/15/2005 steve scully 2 1.8v 3.3v 3.3v 2 2 1.0k 2 10uf cb102 2 1 cb41 .1uf .1uf 1 .1uf 2 cb52 1uf ds3 rb37 1 2 cb81 2 1 cb76 2 1 cb71 2 1 cb64 2 1 cb65 2 1 cb75 2 1 cb69 2 1 cb66 7 11 6 15 14 13 12 5 4 3 2 17 10 ub6 1 2 db1 gnd_tp2 gnd_tpb1 gnd_tp1 gnd_tp3 gnd_tp4 1 2 cb45 2 1 cb100 2 1 cb88 2 1 c9 2 1 cb101 1 2 cb38 1 cb23 1 2 cb73 1 2 cb67 2 1 cb89 2 1 cb70 2 1 c10 2 1 cb55 1 2 cb103 1 2 cb36 1 2 cb50 1 2 cb35 2 1 cb51 2 1 cb86 1 2 cb48 2 cb27 1 cb24 2 1 1 2 cb42 1 2 cb78 2 1 cb77 2 1 cb72 2 1 cb68 1 2 cb37 1 2 cb18 1 2 cb32 1 2 cb57 1 2 cb82 1 cb83 1 2 cb84 1 2 cb87 2 1 cb85 2 1 cb80 2 1 cb26 1 2 cb21 1 2 cb56 1 2 cb79 rb14 2 1 cb2 2 1 cb46 1 cb28 7 11 6 15 14 13 12 5 4 3 2 17 10 ub3 2 1 c5 2 1 cb19 2 1 c7 2 1 c3 7 11 6 15 14 13 12 5 4 3 17 10 ub5 2 1 c8 2 1 rb38 2 1 rb40 1 2 j2 1 h2 1 h1 1 h3 1 h4 2 1 cb31 1 2 cb12 2 1 cb61 2 1 cb59 2 1 cb33 2 1 cb20 1 2 cb7 2 1 c2 2 1 cb54 2 1 cb16 2 1 cb4 2 1 cb10 2 1 cb13 2 1 cb60 2 1 c1 1 2 cb14 2 1 cb11 1 2 cb1 2 1 cb3 1 2 cb58 1 2 cb53 1 2 cb22 2 1 cb6 2 1 1 2 cb49 1 2 cb29 2 1 cb5 .50standoff__nut .50standoff__nut vcc 1uf 1uf 1uf 68uf 1uf 1uf regulator2_output 10uf 68uf .1uf 1uf 68uf 10uf 1uf 1uf .1uf 1uf 68uf 10uf 1 amp 68uf regulator_input 1uf .1uf 1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 10uf 1uf 1uf 1uf 1uf 1uf 1uf 1uf .50standoff__nut 1uf 1uf 1uf 1uf 1uf 1uf 1uf 1uf 0.0 10uf 0.0 68uf regulator1_output regulator_input 10uf 10uf 10uf regulator_input .1uf 1uf 1uf 1uf 1uf 1uf 1uf .1uf vddsyn 1uf 10uf 1uf 1uf 1uf .1uf .1uf 10uf 1uf 1uf 330 green 1uf 1uf 1uf 1uf .50standoff__nut page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 4 4 4 4 v3_3 v3_3 v5_0 v1_8 v3_3 max1793_u in2 out1 out3 set gnd gnd in1 in3 in4 out2 shdn rst out4 v3_3 v3_3 v3_3 v3_3 v5_0 max1793_u in2 out1 out3 set gnd gnd in1 in3 in4 out2 shdn rst out4 max1793_u in2 out1 out3 set gnd gnd in1 in3 in4 out2 shdn rst out4 downloaded from: http:///
@dn_ds26528_dn_lib.dn_ds26528_dn clko_rlf_ltc1 clko_rlf_ltc1 - 9a8 10d6 2b8 @dn_ds26528_dn_lib.dn_ds26528_dn cfg_din cfg_din - 12b4 13a8 @dn_ds26528_dn_lib.dn_ds26528_dn cclk cclk - 13a8 13b6 @dn_ds26528_dn_lib.dn_ds26528_dn bts518 bts518 - 2b8 9b3 @dn_ds26528_dn_lib.dn_ds26528_dn bpclk518 bpclk518 - 2b8 9a7 10a7 cpuclk_out cpuclk_out - 12a6 14b5 @dn_ds26528_dn_lib.dn_ds26528_dn cs0 cs0 - 14b5 15b2 15d2 @dn_ds26528_dn_lib.dn_ds26528_dn cs1_m cs1_m - 12d6 14b5 @dn_ds26528_dn_lib.dn_ds26528_dn cs2_m cs2_m - 12d6 14c5 @dn_ds26528_dn_lib.dn_ds26528_dn cs518 cs518 - 2b2 2b8 @dn_ds26528_dn_lib.dn_ds26528_dn cs_x1 cs_x1 - 2c1 12a5 @dn_ds26528_dn_lib.dn_ds26528_dn d0_spi_miso d0_spi_miso - 2b2 2b3 @dn_ds26528_dn_lib.dn_ds26528_dn d1_spi_mosi d1_spi_mosi - 2b2 2b3 @dn_ds26528_dn_lib.dn_ds26528_dn d2_spi_clk d2_spi_clk - 2a2 2b3 @dn_ds26528_dn_lib.dn_ds26528_dn d5_spi_swap d5_spi_swap - 2b3 9d2 @dn_ds26528_dn_lib.dn_ds26528_dn dat518_<7..0> - 16c4 2a1 12c3 @dn_ds26528_dn_lib.dn_ds26528_dn d6_spi_cpha d6_spi_cpha - 2b3 9c2 @dn_ds26528_dn_lib.dn_ds26528_dn dat518_<7..0> - 16c4 2a1 12c3 @dn_ds26528_dn_lib.dn_ds26528_dn d7_spi_cpol d7_spi_cpol - 2a3 9c2 @dn_ds26528_dn_lib.dn_ds26528_dn dat518_<7..0> - 16c4 2a1 12c3 @dn_ds26528_dn_lib.dn_ds26528_dn dat518_<7..0> dat518_<7..0> - 16c4 2a1 12c3 @dn_ds26528_dn_lib.dn_ds26528_dn digio_en518 digio_en518 - 2b8 9a3 @dn_ds26528_dn_lib.dn_ds26528_dn disinvrx1 disinvrx1 - 5b6 @dn_ds26528_dn_lib.dn_ds26528_dn addr518_<12..0> addr518_<12..0> - 12b3 2b3 base signal synonyms location([zone][dir]) dn_ds26528_dn_lib.dn_ds26528_dn(@dn_ds26528_dn_lib. dn_ds26528_dn(sch_1)) base nets and synonyms for date: apr 17 11:00:30 2006 design: dn_ds26528_dn title: basenet report @dn_ds26528_dn_lib.dn_ds26528_dn disinvrx2 disinvrx2 - 5b2 @dn_ds26528_dn_lib.dn_ds26528_dn disinvrx3 disinvrx3 - 6b6 @dn_ds26528_dn_lib.dn_ds26528_dn disinvrx4 disinvrx4 - 6b2 @dn_ds26528_dn_lib.dn_ds26528_dn disinvrx5 disinvrx5 - 7b6 @dn_ds26528_dn_lib.dn_ds26528_dn disinvrx6 disinvrx6 - 7b2 @dn_ds26528_dn_lib.dn_ds26528_dn disinvrx7 disinvrx7 - 8b6 @dn_ds26528_dn_lib.dn_ds26528_dn disinvrx8 disinvrx8 - 8b2 @dn_ds26528_dn_lib.dn_ds26528_dn disinvtx1 disinvtx1 - 5c6 @dn_ds26528_dn_lib.dn_ds26528_dn disinvtx2 disinvtx2 - 5c2 @dn_ds26528_dn_lib.dn_ds26528_dn disinvtx3 disinvtx3 - 6d6 @dn_ds26528_dn_lib.dn_ds26528_dn disinvtx4 disinvtx4 - 6d2 @dn_ds26528_dn_lib.dn_ds26528_dn disinvtx5 disinvtx5 - 7d6 @dn_ds26528_dn_lib.dn_ds26528_dn disinvtx6 disinvtx6 - 7d2 @dn_ds26528_dn_lib.dn_ds26528_dn disinvtx7 disinvtx7 - 8d6 @dn_ds26528_dn_lib.dn_ds26528_dn disinvtx8 disinvtx8 - 8d2 @dn_ds26528_dn_lib.dn_ds26528_dn done done - 13a8 13b6 @dn_ds26528_dn_lib.dn_ds26528_dn eb0_m eb0_m - 12d6 14d7 15b2 @dn_ds26528_dn_lib.dn_ds26528_dn eb1_m eb1_m - 12d6 14d7 15d2 @dn_ds26528_dn_lib.dn_ds26528_dn flash_vpp flash_vpp - 15a4 14d3 @dn_ds26528_dn_lib.dn_ds26528_dn int518 int518 - 2b8 12a6 14a7 @dn_ds26528_dn_lib.dn_ds26528_dn int518_led int518_led - 12a6 12a2 @dn_ds26528_dn_lib.dn_ds26528_dn jtclk jtclk - 13a8 13d7 13c6 jtdi518_con jtdi518_con - 13d6 2c8 jtdo_spart2con jtdo_spart2con - 13c6 13d6 @dn_ds26528_dn_lib.dn_ds26528_dn @dn_ds26528_dn_lib.dn_ds26528_dn jtclk518 jtclk518 - 13d8 2c8 @dn_ds26528_dn_lib.dn_ds26528_dn jtd518_prom jtd518_prom - 2c8 13a8 13d8 @dn_ds26528_dn_lib.dn_ds26528_dn steve scully 08/15/2005 ds26528dk02a0 17 / 21 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 downloaded from: http:///
once_tclk once_tclk - 14a6 16c3 @dn_ds26528_dn_lib.dn_ds26528_dn once_de_b once_de_b - 14b5 16b1 @dn_ds26528_dn_lib.dn_ds26528_dn oe_m oe_m - 12d6 14d3 15b2 15d2 @dn_ds26528_dn_lib.dn_ds26528_dn mclk518 mclk518 - 9d5 10a7 2b8 @dn_ds26528_dn_lib.dn_ds26528_dn 11b5 11c1 11c5 10a6 led_rlos518_<8..1> led_rlos518_<8..1> - 10b2 10b6 10c2 10 d6 11b1 @dn_ds26528_dn_lib.dn_ds26528_dn 11a5 11c1 11c5 10a4 @dn_ds26528_dn_lib.dn_ds26528_dn once_tdi once_tdi - 14d6 16c3 @dn_ds26528_dn_lib.dn_ds26528_dn once_tdo once_tdo - 14d6 16c3 @dn_ds26528_dn_lib.dn_ds26528_dn once_tms once_tms - 14a6 16c1 @dn_ds26528_dn_lib.dn_ds26528_dn once_trst_b once_trst_b - 14a6 16b2 @dn_ds26528_dn_lib.dn_ds26528_dn osc1544 osc1544 - 12d1 12d7 @dn_ds26528_dn_lib.dn_ds26528_dn osc16348 osc16348 - 12c1 12c7 @dn_ds26528_dn_lib.dn_ds26528_dn oscsocket oscsocket - 12c1 12d4 @dn_ds26528_dn_lib.dn_ds26528_dn osc_mcu osc_mcu - 14a6 15a6 @dn_ds26528_dn_lib.dn_ds26528_dn paddr<15..0> paddr<15..0> - 12a7 @dn_ds26528_dn_lib.dn_ds26528_dn paddr<22..0> - 14a1 @dn_ds26528_dn_lib.dn_ds26528_dn paddr<17..1> - 15a3 15c3 @dn_ds26528_dn_lib.dn_ds26528_dn paddr<22..0> paddr<22..0> - 14a1 @dn_ds26528_dn_lib.dn_ds26528_dn paddr<17..1> paddr<22..0> - 14a1 @dn_ds26528_dn_lib.dn_ds26528_dn paddr<17..1> - 15a3 15c3 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<31..0> pdata<31..0> - 14a2 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<31..16> - 12c7 12d6 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<31..24> - 15a1 @dn_ds26528_dn_lib.dn_ds26528_dn led_rlf518_<8..1> led_rlf518_<8..1> - 10b2 10b6 10c2 10d6 11a1 jtrst518 jtrst518 - 13d7 2c8 @dn_ds26528_dn_lib.dn_ds26528_dn jtms518 jtms518 - 13d8 2c8 @dn_ds26528_dn_lib.dn_ds26528_dn jtms jtms - 13a8 13d7 13c6 @dn_ds26528_dn_lib.dn_ds26528_dn jtd_prom2spart jtd_prom2spart - 13a6 13c6 @dn_ds26528_dn_lib.dn_ds26528_dn @dn_ds26528_dn_lib.dn_ds26528_dn pdata<16> pdata<16> - 15d7 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<23..16> pdata<31..0> - 14a2 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<23..16> - 15c1 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<31..16> - 12c7 12d6 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<31..16> pdata<31..0> - 14a2 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<31..16> - 12c7 12d6 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<31..24> - 15a1 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<17> pdata<17> - 15d7 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<18> pdata<18> - 15c7 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<19> pdata<19> - 15c7 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<21> pdata<21> - 15d7 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<22> pdata<22> - 15c7 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<23> pdata<23> - 15c7 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<31..24> pdata<31..0> - 14a2 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<31..16> - 12c7 12d6 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<31..24> - 15a1 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<26> pdata<26> - 15d7 @dn_ds26528_dn_lib.dn_ds26528_dn pdata<28> pdata<28> - 15c7 @dn_ds26528_dn_lib.dn_ds26528_dn pqa0 pqa0 - 14d6 @dn_ds26528_dn_lib.dn_ds26528_dn pqa1 pqa1 - 14d6 @dn_ds26528_dn_lib.dn_ds26528_dn pqa3 pqa3 - 14d6 @dn_ds26528_dn_lib.dn_ds26528_dn pqa4 pqa4 - 14d6 @dn_ds26528_dn_lib.dn_ds26528_dn pqb0 pqb0 - 14d7 @dn_ds26528_dn_lib.dn_ds26528_dn pqb1 pqb1 - 14d7 @dn_ds26528_dn_lib.dn_ds26528_dn pqb2 pqb2 - 14d7 @dn_ds26528_dn_lib.dn_ds26528_dn pqb3 pqb3 - 14d7 @dn_ds26528_dn_lib.dn_ds26528_dn steve scully 08/15/2005 ds26528dk02a0 17 / 21 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 downloaded from: http:///
refclk518 refclk518 - 2b8 9a7 10a7 @dn_ds26528_dn_lib.dn_ds26528_dn rd_ds518 rd_ds518 - 12a4 2b8 @dn_ds26528_dn_lib.dn_ds26528_dn rd#usb rd#usb - 12a5 16c4 @dn_ds26528_dn_lib.dn_ds26528_dn rcon rcon - 14d3 15b8 11d8 10d4 10d8 11b4 11b8 11d4 @dn_ds26528_dn_lib.dn_ds26528_dn 4c4 4c8 9c7 10c4 10c8 @dn_ds26528_dn_lib.dn_ds26528_dn regulator1_output regulator1_output - 17d7 @dn_ds26528_dn_lib.dn_ds26528_dn regulator2_output regulator2_output - 17c7 @dn_ds26528_dn_lib.dn_ds26528_dn reset_b reset_b - 14b5 15b5 16c3 2b8 13c7 @dn_ds26528_dn_lib.dn_ds26528_dn rm518_<8..1> rm518_<8..1> - 3a4 3a8 3c4 3c8 4a4 4a8 @dn_ds26528_dn_lib.dn_ds26528_dn 4c4 4c8 10b4 10b8 10c4 10c8 11a4 11a8 11c4 11c8 rring518_<8..1> rring518_<8..1> - 3b4 3b8 3d4 3d8 4b4 4b8 @dn_ds26528_dn_lib.dn_ds26528_dn 4d4 4d8 5b4 5b8 6b4 6b8 7b4 7b8 8b4 8b8 rser518_<8..1> rser518_<8..1> - 3a4 3a8 3c4 3c8 4a4 4a8 @dn_ds26528_dn_lib.dn_ds26528_dn 4c4 4c8 9b7 10b8 10c4 10d4 10d8 11b4 11b8 11d4 11d8 rsig518_<8..1> rsig518_<8..1> - 3a4 3a8 3c4 3c8 4a4 4a8 @dn_ds26528_dn_lib.dn_ds26528_dn 4c4 4c8 10b4 10b8 10c4 10c8 11b4 11b8 11c4 11c8 rsync518_<8..1> rsync518_<8..1> - 3a4 3a8 3c4 3c8 4a4 4a8 @dn_ds26528_dn_lib.dn_ds26528_dn 4c4 4c8 9a5 10b4 10b8 10d4 10d8 11b4 11b8 11c4 11c8 rsysclk518_<8..1> rsysclk518_<8..1> - 10b2 10b6 10c2 10c6 11b1 @dn_ds26528_dn_lib.dn_ds26528_dn 11b5 11c1 11c5 3a4 3a8 3c4 3c8 4a4 4a8 4c4 4c8 9d6 rtip518_<8..1> rtip518_<8..1> - 3b4 3b8 3c4 3c8 4b4 4b8 @dn_ds26528_dn_lib.dn_ds26528_dn 4c4 4c8 5b4 5b8 6b4 6b8 7b4 7b8 8b4 8b8 rw_m rw_m - 12d6 14d3 @dn_ds26528_dn_lib.dn_ds26528_dn rxf#usb rxf#usb - 12a5 16c4 @dn_ds26528_dn_lib.dn_ds26528_dn rclk518_<8..1> rclk518_<8..1> - 3a4 3a8 3c4 3c8 4a4 4a8 @dn_ds26528_dn_lib.dn_ds26528_dn 4c4 4c8 10b4 10b8 10c4 rchbk518_<8..1> rchbk518_<8..1> - 3a4 3a8 3c4 3c8 4a4 4a8 @dn_ds26528_dn_lib.dn_ds26528_dn pwren#usb pwren#usb - 12a5 16b4 @dn_ds26528_dn_lib.dn_ds26528_dn prt1_out prt1_out - 16a8 16b8 @dn_ds26528_dn_lib.dn_ds26528_dn prt1_in prt1_in - 16a8 16b8 10c8 11b4 11b8 11c4 11c8 scanen518 scanen518 - 2c8 9b2 @dn_ds26528_dn_lib.dn_ds26528_dn scanmo518 scanmo518 - 2c8 9b3 @dn_ds26528_dn_lib.dn_ds26528_dn sci1_in sci1_in - 14b8 16b8 @dn_ds26528_dn_lib.dn_ds26528_dn sci1_out sci1_out - 14b8 16b8 @dn_ds26528_dn_lib.dn_ds26528_dn sci2_in sci2_in - 14b8 @dn_ds26528_dn_lib.dn_ds26528_dn sci2_out sci2_out - 14b8 @dn_ds26528_dn_lib.dn_ds26528_dn si_wuusb si_wuusb - 12a5 16c4 @dn_ds26528_dn_lib.dn_ds26528_dn spisel_al_flos1 spisel_al_flos1 - 10d6 2b8 9c3 @dn_ds26528_dn_lib.dn_ds26528_dn spi_miso spi_miso - 2b2 14a6 @dn_ds26528_dn_lib.dn_ds26528_dn spi_mosi spi_mosi - 2b2 14a7 @dn_ds26528_dn_lib.dn_ds26528_dn spi_sck spi_sck - 2b2 14b5 @dn_ds26528_dn_lib.dn_ds26528_dn spi_ss spi_ss - 2b2 14b5 @dn_ds26528_dn_lib.dn_ds26528_dn tchbk518_<8..1> tchbk518_<8..1> - 3a1 3a5 3c1 3c5 4a1 4a5 @dn_ds26528_dn_lib.dn_ds26528_dn 4c1 4c5 10b4 10b8 10c4 10c8 11b4 11b8 11c4 11c8 tclk518_<8..1> tclk518_<8..1> - 3a1 3a5 3c1 3c5 4b1 4b5 @dn_ds26528_dn_lib.dn_ds26528_dn 4c1 4c5 9c4 10c4 10c8 10d4 10d8 11b4 11b8 11d4 11d8 tim_16h_8l tim_16h_8l - 14d7 15b8 @dn_ds26528_dn_lib.dn_ds26528_dn tring518_<8..1> tring518_<8..1> - 3b1 3b5 3d1 3d5 4b1 4b5 @dn_ds26528_dn_lib.dn_ds26528_dn 4d1 4d5 5c4 5c8 6c4 6c8 7c4 7c8 8c4 8c8 tser518_<8..1> tser518_<8..1> - 3a1 3a5 3c1 3c5 4a1 4a5 @dn_ds26528_dn_lib.dn_ds26528_dn 4c1 4c5 9b4 10b4 10b8 10d4 10d8 11b4 11b8 11c4 11c8 tsig518_<8..1> tsig518_<8..1> - 3a1 3a5 3c1 3c5 4a1 4a5 @dn_ds26528_dn_lib.dn_ds26528_dn 4c1 4c5 10b4 10b8 10c4 10c8 11b4 11b8 11c4 11c8 tssync518 tssync518 - 9d6 10a7 2a8 @dn_ds26528_dn_lib.dn_ds26528_dn tsync518_<8..1> tsync518_<8..1> - 3a1 3a5 3c1 3c5 4a1 4a5 @dn_ds26528_dn_lib.dn_ds26528_dn 4c1 4c5 9d5 10b4 10b8 10d4 10d8 11b4 11b8 11c4 11c8 tsysclk518_<8..1> tsysclk518_<8..1> - 3a1 3a5 3c1 3c5 4a1 4 a5 @dn_ds26528_dn_lib.dn_ds26528_dn 4c1 4c5 10b2 10b6 10c2 10c6 11b1 11b5 11c1 11c5 17 / 21 ds26528dk02a0 08/15/2005 steve scully page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 downloaded from: http:///
@dn_ds26528_dn_lib.dn_ds26528_dn x_init x_init - 12a7 13a8 @dn_ds26528_dn_lib.dn_ds26528_dn xtal xtal - 14a6 15a6 @dn_ds26528_dn_lib.dn_ds26528_dn xrst xrst - 13a8 13c5 @dn_ds26528_dn_lib.dn_ds26528_dn wr_rw518 wr_rw518 - 12a5 2b8 @dn_ds26528_dn_lib.dn_ds26528_dn wrusb wrusb - 12a5 16c4 @dn_ds26528_dn_lib.dn_ds26528_dn @dn_ds26528_dn_lib.dn_ds26528_dn txena518 txena518 - 2a8 9a2 @dn_ds26528_dn_lib.dn_ds26528_dn txe#usb txe#usb - 12a5 16c4 7d4 7d8 8d4 8d8 @dn_ds26528_dn_lib.dn_ds26528_dn 4c1 4c5 5d4 5d8 6d4 6d8 ttip518_<8..1> ttip518_<8..1> - 3a5 3b1 3c1 3c5 4b1 4b5 9a6 vddsyn vddsyn - 14d2 17c5 steve scully 08/15/2005 ds26528dk02a0 17 / 21 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 downloaded from: http:///

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